This invention relates to switching apparatus for digital signals.
In a video production facility, it is known to route video signals from signal sources, such as cameras, VTRs etc., to signal receivers, such as video effects devices; monitors and VTRs using an n.times.m switching matrix having a set of n input terminals connected to respective signal sources and a set of m output terminals connected to respective signal receivers. The switching matrix can be configured so that any one of the n input terminals can be connected to any subset of the m output terminals, including a single output terminal. In this fashion, a video signal received at input terminal A, for example, can be distributed to all the receivers connected to the specified subset of output terminals. If, then, it is desired to connect input terminal B, which receives a different video signal, to the subset of output terminals, the configuration of the matrix can be changed so that input terminal B is connected to the subset of output terminals in lieu of input terminal A.
If a switching matrix switches from selecting input terminal A to selecting input terminal B, but the two video signals provided by the sources connected to those terminals are not synchronous, the synchronization circuits of the receivers connected to the output terminals might not lock immediately to the new video signal. In the case of the receiver being a monitor, the temporary loss of synchronization might be manifested by a rolling or jumping of the picture displayed on the monitor. In order to alleviate this problem, it is conventional to maintain tight synchronism between video signals received at the input terminals of a switching matrix. In a conventional switching matrix, it is usual to maintain the input signals in synchronism to within one degree of the subcarrier cycle, or about 700 ps. Because of differences in path length through the matrix, previously it has also been necessary to synchronize propagation of signals through the core of the switching matrix.
Video switchers are designed to keep track of the instantaneous location in the video frame of the signal passing through the switcher. This enables the switcher always to switch in the vertical interval of the video signal, so as to minimize visual disturbance to the viewer of a display based on the video signal. In switchers designed for use with signals in the NTSC system, switching normally takes place during line 10 of the video frame. The constraints that are imposed on relative timing of the video signals and on the timing of the switching operation ensure that the degradation of the video signal on a switch is kept quite small.
It is common to distribute video signals in a production facility in serial digital form. In a known serial digital video format, the composite analog video signal is sampled at a frequency of 14.3 MHz so that each video line is resolved into 910 samples, 768 of which occur during the active interval. Each sample value is quantized to ten bits, so that the bit rate is 143 Mbits/s. A frame alignment word (FAW) is inserted at the end of the active interval of each video line of the serial digital composite video signal, each serial digital video line being a data frame of a nominal duration. The FAW, which is known as the timing reference signal (TRS), may be a sequence of bits that cannot occur, or is very unlikely to occur, in ten-bit digital composite video, and may be a 40-bit sequence.
In a serial digital composite video signal, the TRS occurs at the same frequency as the horizontal sync pulse in an analog video signal. If the TRS occurs too early or too late relative to the previous TRS, the display provided by the signal is degraded. In order to perform a synchronous switch between two serial digital composite video signals, it is necessary that the interval between successive TRS's of the output signal remain constant. This implies that the relative timing difference of the signals being switched must be constrained to a time not exceeding one quarter of the bit period. For serial digital composite video signals, this corresponds to a time of from 900 to 1750 picoseconds.
Previous methods of maintaining proper timing of analog video signals or parallel digital video signals at the output of a switching matrix have involved adjusting the timing at the input terminals of the switching matrix in order to achieve bit synchronicity at the inputs, but with high speed signals the variations in path lengths through the matrix can introduce delay differences that are not acceptable.